Phase 2 · Next
Hardware acceleration
The same compact detection models compiled onto reconfigurable chips.
The physics problem
Inline inspection is a tax on every request. Serving a detection model on a GPU means buying GPU-shaped infrastructure to run something computationally small, then paying again for every request that arrives.
Reconfigurable chips are a better fit for a classifier than a GPU is: streamlined logic at low precision, rather than general-purpose floating-point hardware.
The target
Line-rate inspection, with order-of-magnitude improvements in latency, power and cost per request. Reprogrammable as threats change — fixed-function silicon would be obsolete the moment the attack surface moved.
The compression and quantization work is the on-ramp: the toolchain that shrinks a model is the one that prepares it for hardware.